Analog Layout Lead, Silicon Engineering

Onsite$178,000 - $250,000/yrPosted today

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Job details

Location: Sunnyvale or Burlingame
Work type: Onsite
Compensation: $178,000 - $250,000/yr
Posted: today
Apply on: metacareers.com

About this role

Meta's Silicon Engineering organization is building custom silicon solutions that power the next generation of virtual and augmented reality products, including wearable devices and spatial computing platforms. We are seeking an experienced Analog Layout Lead to drive the physical implementation of complex analog and mixed-signal circuits for custom chips at the heart of Meta's reality labs hardware portfolio. In this role, you will own the full-custom layout of high-performance analog blocks, define physical design methodologies, and partner closely with circuit design and verification teams to deliver silicon that meets aggressive power, performance, and area targets.

Responsibilities

Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms
Define and enforce analog layout methodologies, design rules, and best practices across the physical design team
Drive parasitic-aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed-signal designs
Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results
Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes
Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts
Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology
Partner with process technology and design kit teams to evaluate new process nodes and contribute to PDK qualification for analog layout
Identify and resolve layout-induced performance issues through post-layout simulation analysis and iterative design refinement
Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs
Manage layout contractors to deliver high-quality final GDS on schedule and in alignment with design specifications

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes (28nm or below)
8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification
Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out
Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed-signal environments
Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints and implementation decisions
Experience managing and mentoring layout engineers and coordinating work with external contractors

Preferred Qualifications

Familiarity with post-layout simulation flows including RC extraction and back-annotated verification using tools such as Spectre or Calibre
Experience contributing to or evaluating process design kits and design rule documentation for new process node bring-up
Experience with analog layout for consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical
Experience with 3D stacking technologies and advanced packaging layout considerations
Track record of developing reusable analog layout templates or parameterized cells that improve team-wide layout efficiency and consistency

Compensation

$178,000/year - $250,000/year; Country: US; Bonus eligible; Equity eligible

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

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Equal Opportunity

Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.

Accommodations

Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

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