Nvidia
Santa Clara, California
ASIC Design Efficiency Engineer
Job details
- Location
- Santa Clara, California
- Work type
- Onsite
- Compensation
- $116,000 - $218,500/yr
- Posted
- Apr 24, 2026
- Apply on
- nvidia.wd5.myworkdayjobs.com
About this role
Bachelors in EE or CE or equivalent experience; 2+ years; SystemVerilog/HDL; strong logic design and computer architecture; good collaboration skills.
What you'll do at Nvidia:
- Develop designs
- Verify RTL
- Collaborate teams
Apply to this ASIC Design Efficiency Engineer role at Nvidia with a tailored resume on ApplyBolt.