ASIC Design Engineer

Bachelors +7 yrs OR Masters +4 yrs OR PhD +1 yr; ASIC tapeout experience; strong Verilog/SystemVerilog RTL; timing, power, and area optimization; ASIC design flows; debugging.

What you'll do at Cisco:

• design RTL
• verify timing
• collaborate with teams

Apply to this ASIC Design Engineer role at Cisco with a tailored resume on ApplyBolt.