ASIC Design Engineer III

Bachelor's with 5-7 yrs or Master's with 3-5 yrs or PhD with 0-2 yrs; Secret clearance; 3+ yrs VHDL targeting Xilinx; 3 yrs Cadence Virtuoso; 5 yrs VHDL/Verilog; 3 yrs ModelSim/QuestaSim.

What you'll do at Arcfield:

• designing ASIC
• verifying HDL
• porting RTL

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