Palo Alto Networks
Santa Clara, California
ASIC Design Verification Engineer
Job details
- Location
- Santa Clara, California
- Work type
- Onsite
- Compensation
- $106,400 - $172,150/yr
- Visa
- Sponsorship available
- Posted
- Apr 8, 2026
- Apply on
- paloaltonetworks.wd5.myworkdayjobs.com
About this role
BS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
What you'll do at Palo Alto Networks:
- defining tests
- developing test benches
- planning coverage
Apply to this ASIC Design Verification Engineer role at Palo Alto Networks with a tailored resume on ApplyBolt.