ASIC/SoC Silicon Test Engineer
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Apply to ASIC/SoC Silicon Test Engineer at GoogleJob details
- Location
- Sunnyvale, California
- Work type
- Onsite
- Compensation
- $163,000 - $236,000/yr
- Posted
- today
- Apply on
- careers.google.com
About this role
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
- 5 years of experience in test engineering or product engineering.
- Experience in ASIC or SoC test development, bring-up, or debug.
Preferred qualifications:
- Master's degree in Computer Science, Electrical Engineering, or related technical field, or equivalent practical experience.
- 10 years of experience in test engineering, product engineering, or silicon quality/reliability.
- Experience with scan/ATPG test development or memory BIST test development and repair implementation.
- Experience testing IPs such as Phase-Locked Loops (PLLs), PVT sensors, temperature sensors, Process Monitor Ring Oscillator (PMRO), and eFuse.
- Familiarity with Automatic Test Equipment (ATE) from Advantest and Teradyne, (e.g., V93000, 6007, UltraFlex, Titan, etc.).
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Google’s data centers are some of the most advanced in the world. In this role, you will help build the SoCs that power these data centers by driving development of comprehensive ATE test solutions for high volume manufacturing. You'll create silicon and follow it into the field to close the loop back to design and test for the next generations of chips. You'll help to integrate SoC technologies into devices and drive ATE manufacturing testing to validate performance and screen bad devices. You will work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Develop and drive implementation of silicon test requirements with internal design teams and external vendors.
- Participate in developing and executing strategies for SoC product NPI, bring-up, verification, characterization, and qualification support, including bench test, troubleshooting, test coverage optimization, new product defective parts per million correlation, and product correlation between system and ATE.
- Leverage ATE test experience and expertise to drive quality improvements.
- Collaborate with design, DFT, and quality teams to drive best practices for post-silicon testing.
- Provide back-stop support for chip production, including test program upgrade and release procedures, volume data analytics, test time reduction, yield improvement, and Return Merchandise Authorization (RMA) analysis.