Design Engineering Intern

At Silicon Labs, our internship program offers students the opportunity to do meaningful, hands-on work that directly impacts the future of connected devices. As an intern, you’ll contribute to real projects, collaborate with world-class engineers, and gain exposure to the full product lifecycle, from research and design to testing and integration. Our program also includes professional development workshops, networking events, and mentorship to help you grow both technically and professionally. Our goal is to help you build on your skills, gain hands-on experience, and explore the potential of a future career with Silicon Labs.

Meet the Team

You’ll join the Modem Verification (IP Verification) team, which ensures the quality and reliability of Silicon Labs’ ASIC IP used in IoT applications. The team focuses on verifying complex digital designs for modem systems, applying advanced verification techniques to guarantee robust performance across real-world wireless scenarios. This critical work helps deliver low-power, high-performance solutions trusted across a wide range of connected devices.

Responsibilities

• Contribute to the verification of ASIC IP blocks used in wireless modem designs for IoT applications.
• Apply Verilog or SystemVerilog to develop testbenches, simulations, and verification environments.
• Use C programming and scripting skills to support automated testing and verification flows.
• Assist in identifying and debugging design or verification issues in collaboration with senior engineers.
• Document results, share progress, and propose improvements to existing methodologies.

Skills You Need

Minimum Qualifications:

• Currently pursuing a Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Exposure to Verilog or SystemVerilog for digital design and verification.
• Proficiency in C programming and scripting (e.g., Python, Perl, or similar).
• Coursework in telecommunications basics, digital design, VLSI, or embedded programming.
• Hands-on project or lab experience in digital design verification or FPGA prototyping.

The following qualifications will be considered a plus:

• Knowledge of UVM (Universal Verification Methodology).
• Exposure to AI through professional experience and/or academic research
• Experience with verification debug techniques and tools.
• Prior exposure to verification environments for digital communication systems.