Design Validation Engineering Intern
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About this role
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
The role: Design Validation Engineering Intern
Hybrid, working onsite at our Santa Clara office 3 days per week.
12 Week Program: June 1st - August 21st or June 22nd - September 11th
Location: Onsite at our Santa Clara, CA headquarters 5 days per week.
What You Will Do:
- Development of tools and methodologies for silicon validation:
- Automation of data collection
- Instrument control interface
- Database back end including outlier detection and classification
- Data post processing and analysis for margining and debug
- Linear and logical regression, clustering, plot and report generation
- Work with high speed serial interfaces including PCI Express Gen5, LPDDR5 memory, and die to die interconnections on multi-chip module
What you will bring:
- Familiarity with hardware systems, advanced electronic circuits, signals and systems
- Lab coursework and/or experience
- Solid knowledge and understanding of probability and statistical science
- Strong C and Python programming skills
- Excellent verbal and written communication skills
- Attending graduating year of graduate school program