Intel
Folsom or San Jose or Santa Clara
Design Verification Engineer
Job details
- Location
- Folsom or San Jose or Santa Clara
- Work type
- Onsite
- Compensation
- $141,910 - $269,100/yr
- Posted
- 2 weeks ago
- Apply on
- intel.wd1.myworkdayjobs.com
About this role
Bachelor’s in EE/CE/CS with 6+ years experience; or Master’s with 4+; or PhD with 2+; strong SystemVerilog, UVM, IP verification, and DDR/DDR PHY knowledge preferred.
What you'll do at Intel:
- Verify IP
- Develop benches
- Debug issues
Apply to this Design Verification Engineer role at Intel with a tailored resume on ApplyBolt.