Intern - Design Architecture, HBM

The HBM Design Architecture team drives exploration and analysis of next‑generation AI memory and system environments. The organization partners closely with DTPCO, Design, and Product/System teams to understand how evolving AI workloads shape memory system behavior and architectural strategies.

The HBM Design Architecture Intern supports early‑stage research, performance modeling, and tool development that guide future HBM architectural decisions. This role provides hands‑on exposure to AI system trends and memory subsystem analysis while working closely with senior engineers and technical mentors.

Responsibilities

• Research emerging trends in compute, networking, and storage infrastructure to understand how future AI workloads may evolve.
• Support HBM architecture analysis by gathering and synthesizing data related to bandwidth, latency, and system‑level memory requirements.
• Help develop or refine simulation frameworks used to model AI cluster performance and memory subsystem behavior.
• Participate in building trend dashboards using CSP benchmarks and industry datasets.
• Collaborate with DTPCO mentors to explore architectural intercept opportunities for next‑generation AI systems.

Minimum Qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Foundational understanding of computer architecture, digital systems, and hardware/software interaction.
• Programming experience in Python, C/C++, or similar languages.
• Ability to learn new tools, simulation frameworks, and data‑analysis workflows.

Preferred Qualifications

• Exposure to AI workload behavior, ML training pipelines, or large‑scale system bottlenecks.
• Ability to translate research findings into concise technical summaries or recommendations.