Intel
Santa Clara, California
Logic Design Engineer
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Apply to Logic Design Engineer at IntelJob details
- Location
- Santa Clara, California
- Work type
- Hybrid
- Compensation
- $220,920 - $311,890/yr
- Clearance
- Other
- Posted
- 5 days ago
- Apply on
- intel.wd1.myworkdayjobs.com
About this role
BSEE or BScE with 8+ years (or MS with 6+ years); 5+ years SerDes design experience; System Verilog/RTL, OVM/UVM, post-silicon validation, microarchitecture, and strong communication; scripting (TCL/Perl/Python/Ruby) preferred.
What you'll do at Intel:
- designing logic
- coding RTL
- supporting integration
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