Manager, ASIC Design Engineering (Starshield Satellite Engineering)

Lead ASIC/FPGA design team; RTL/Verilog; 5+ years RTL/FPGA/ASIC; 2+ years management; Bachelor's in engineering.

What you'll do at SpaceX:

• Lead design
• Define architecture
• Mentor team

Apply to this Manager, ASIC Design Engineering (Starshield Satellite Engineering) role at SpaceX with a tailored resume on ApplyBolt.