Intel
Santa Clara or Phoenix or Hillsboro
Principal Analog Circuit Design Engineer - SerDes
Job details
- Location
- Santa Clara or Phoenix or Hillsboro
- Work type
- Hybrid
- Compensation
- $220,920 - $311,890/yr
- Posted
- Apr 30, 2026
- Apply on
- intel.wd1.myworkdayjobs.com
About this role
Master’s in Electrical or Electronics Engineering; 8+ years analog/mixed-signal high-speed SerDes design; experience with PLL/CTLE/DFE/ADC/TX; PCIe Gen5/Gen6 and 100G/400G/800G Ethernet; FinFET CMOS 7nm or below; Cadence Virtuoso/ADE, HSPICE; silicon bring-up and post-silicon validation.
What you'll do at Intel:
- lead design
- mentor engineers
- validate circuits
Apply to this Principal Analog Circuit Design Engineer - SerDes role at Intel with a tailored resume on ApplyBolt.