Intel
Hillsboro or Santa Clara or Austin
Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Job details
- Location
- Hillsboro or Santa Clara or Austin
- Work type
- Hybrid
- Compensation
- $141,910 - $200,340/yr
- Visa
- Sponsorship available
- Posted
- 3 weeks ago
- Apply on
- intel.wd1.myworkdayjobs.com
About this role
Master's degree in electrical engineering or related field; 5+ years in physical/layout design, advanced nodes; proficiency with layout tools; floorplanning and design verification.
What you'll do at Intel:
- developing layout
- converging design
Apply to this Senior Testchip SoC Physical Design Engineer (Integration & Methodology) role at Intel with a tailored resume on ApplyBolt.