Silicon Validation Engineer, Infra Silicon

Responsibilities

• Define and own the end-to-end silicon validation strategy for custom infrastructure ASICs and SoCs, spanning pre-silicon simulation correlation through post-silicon characterization and production qualification
• Lead silicon bring-up activities including power sequencing validation, clock and reset verification, and early functional debug on first-pass hardware
• Architect scalable automated test infrastructure for functional validation, performance benchmarking, and reliability screening of custom silicon in lab and data center environments
• Drive correlation between pre-silicon simulation models and post-silicon measurements to close coverage gaps and improve future design-for-test methodologies
• Establish silicon characterization programs covering voltage-frequency optimization, thermal profiling, and margin analysis to define production operating points
• Partner with RTL design, physical design, and firmware teams to define testability requirements, debug interfaces, and built-in self-test strategies early in the design cycle
• Lead root cause analysis of silicon failures using logic analyzers, oscilloscopes, JTAG, and internal scan infrastructure, and drive corrective actions with design teams
• Define and track silicon validation milestones, risk assessments, and readiness criteria for tape-out, bring-up, and production release gates
• Develop and publish silicon validation best practices, methodologies, and reusable frameworks that improve efficiency across multiple concurrent chip programs
• Provide technical leadership and mentorship to other engineers across the silicon validation organization, influencing long-term roadmap and team capability development

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 12+ years of experience in post-silicon validation, silicon bring-up, or hardware characterization of custom ASICs or SoCs
• Experience defining and executing validation strategies across the full silicon lifecycle, from first silicon bring-up through production qualification
• Experience with digital design fundamentals including RTL, timing analysis, clock domain crossing, and power delivery as they relate to post-silicon debug
• Experience developing automated test frameworks and validation infrastructure for high-volume silicon screening in lab or data center environments
• Depth of expertise in SW/FW development (Python, C/C++)
• Experience leading cross-functional technical programs spanning design, firmware, and systems engineering teams with demonstrated organizational impact

Preferred Qualifications

• Track record of driving silicon validation methodology improvements that measurably reduced time-to-production or improved yield across multiple chip generations
• Experience validating custom silicon for hyperscale data center applications such as compute accelerators, network ASICs, or storage controllers
• Experience with design-for-test methodologies including scan insertion, BIST, and JTAG boundary scan as applied to complex SoC validation
• Familiarity with high-speed interface validation including PCIe, Ethernet, HBM, or DDR characterization and compliance testing

Compensation

• $212,000/year - $294,000/year; Country: US; Bonus eligible; Equity eligible

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