SOC Physical Design Static Timing Analysis Engineer

Bachelor's/Master's/PhD in EE/CE/CS; 7+ yrs SOC timing analysis; 3+ yrs tools; TCL scripting; timing constraints; clock network; PVT; cross-team collaboration.

What you'll do at Intel:

• analyze timing
• optimize clock
• define constraints

Apply to this SOC Physical Design Static Timing Analysis Engineer role at Intel with a tailored resume on ApplyBolt.