Advanced Packaging & Physical Integration Intern - Advanced Packaging & Physical Integration

## Your Team, Your Impact The AI era has fundamentally changed what a semiconductor package is. A package is no longer a container for a chip — it is the architecture. As AI accelerators push beyond the reticle limit of any single die, the package has become the integration layer where compute silicon, high-bandwidth memory, optical I/O, and die-to-die interconnects are assembled into a unified system. At Marvell, the advanced packaging team is where that integration happens — for the custom XPUs, AI accelerators, and high-speed connectivity platforms that the world's largest hyperscalers depend on to scale their AI infrastructure. ## What You Can Expect As our Ph.D. Advanced Packaging & Physical Integration Intern, every day you will work on packaging design and analysis challenges tied directly to production AI accelerator and connectivity platforms. Specifically, you can expect to: - Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces — including 224G SerDes, die-to-die interconnects, and HBM interfaces — across multi-die package substrates and interposers - Develop and execute thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages, evaluating heat dissipation, warpage, and reliability under production conditions - Contribute to physical design and layout of package substrates, RDL interposers, and chiplet integration schemes for custom AI accelerator platforms - Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions against silicon measurements and production data - Use industry-standard EDA and simulation tools — including Ansys, Cadence Sigrity, or equivalent — to model and optimize package-level electrical, thermal, and mechanical performance - Present analysis results and design recommendations to the engineering team and contribute to packaging design reviews ## What We're Looking For To thrive in this role, you must have hands-on research experience in semiconductor packaging, signal integrity, or a closely related physical design discipline. Specifically: - Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field, with a research focus in advanced packaging, signal/power integrity, thermal engineering, or heterogeneous integration - Demonstrate research or project experience in one or more of the following: package-level SI/PI analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization - Apply strong fundamentals in electromagnetics, heat transfer, or materials mechanics — sufficient to build and interpret simulation models that inform real packaging design decisions - Use simulation tools relevant to your research area (Ansys HFSS, Ansys Icepak, Cadence Sigrity, or equivalent) with confidence and independence - Communicate analysis results and design tradeoffs clearly — you will present your work to the engineering team and defend your recommendations