Architecture, DSP & Systems Architecture Ph.D. Intern

## What You Can Expect As our Ph.D. Architecture, DSP & Systems Intern, every day you will work on systems-level problems that sit at the boundary of research and production — where the algorithms and architectures you develop have direct consequences for how AI infrastructure performs at scale. Specifically, you can expect to: - Architect, model, and evaluate system-level designs for switching, interconnect, or DSP applications — developing analytical models and simulations that inform real silicon architecture decisions - Develop and optimize DSP algorithms for high-speed electrical or optical links, including equalization, FEC, timing recovery, and signal integrity techniques for PAM4, coherent, or emerging modulation formats - Design and analyze network architectures for AI fabrics — including forwarding pipeline design, congestion control, traffic management, and load balancing for scale-up, scale-out, and scale-across applications - Collaborate with analog, digital, and software engineering teams to validate architectural assumptions against real hardware and silicon measurements - Build behavioral models and simulations in MATLAB, Python, or C++ to evaluate performance tradeoffs across architecture, power, latency, and bandwidth - Present architectural proposals and algorithm results to engineering leadership and contribute to internal technical documentation and design reviews ## What We're Looking For To thrive in this role, you must have hands-on research experience in computer architecture, DSP, or networking systems — with the ability to move fluidly between theory and implementation. Specifically: - Currently enrolled in a Ph.D. program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a research focus in computer architecture, digital signal processing, communications systems, or networking - Demonstrate research experience in one or more of the following: processor or switch architecture, DSP algorithm design for high-speed communications, network protocol design, or system-level modeling and simulation - Apply strong analytical fundamentals — whether in signal processing theory, queuing theory, information theory, or computer architecture — to real engineering problems with measurable performance targets - Model and simulate complex systems using tools such as MATLAB, Python, or C/C++; familiarity with hardware description languages (Verilog, SystemVerilog) or cycle-accurate simulation is a plus - Communicate architectural decisions and algorithm tradeoffs clearly — you will present your work to engineering teams and defend your approach against real system constraints ## Preferred Qualifications - Familiarity with Ethernet switching architectures, programmable forwarding pipelines, or network congestion control algorithms for large-scale AI fabrics - Experience with PAM4, coherent, or high-speed serial link DSP — including equalization, FEC, or timing and synchronization algorithms - Exposure to custom compute architecture, SoC design, or XPU/GPU interconnect systems - Knowledge of Ultra Ethernet Consortium (UEC) protocols, RoCE, or RDMA networking for AI workloads - Experience with open networking platforms such as SONiC or P4-based programmable pipelines