ASIC Design-for-Test (DFT) Engineer Intern

Keysight Technologies is a technology company delivering solutions in electronic design, simulation, prototyping, testing, manufacturing, and optimization. The ASIC Design-for-Test Engineer Intern will support DFT architecture development and verification, ATPG pattern generation, test analysis, automation, silicon validation, and collaboration across ASIC engineering teams.

What you'll do:

• Support the development and verification of DFT architectures for complex digital and mixed-signal ASICs
• Learn and apply industry-standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)
• Assist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent and other industry-standard EDA tools
• Develop scripts and automation solutions using Python, Ruby, Tcl, or similar languages to improve engineering workflows and data analysis
• Collaborate with ASIC design, verification, physical design, and product engineering teams to ensure testability requirements are incorporated throughout the design lifecycle
• Participate in silicon bring-up, characterization, debug, and failure analysis activities
• Analyze test results and help develop solutions to improve test quality, coverage, and efficiency

What they're looking for:

• Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
• Completion of sophomore year or higher by Summer 2027
• Coursework in Digital Logic Design, Computer Architecture, VLSI Design, FPGA Design, or related areas
• Understanding of digital circuits, finite state machines, and computer hardware fundamentals
• Programming or scripting experience in Python, C/C++, Tcl, Ruby, or similar languages
• Strong analytical, problem-solving, and debugging skills
• Demonstrated ability to work effectively in a collaborative team environment
• Candidates who wish to be considered must be enrolled in a accredited college/university as of September 2027
• Applicants who have graduated before September 2027 will not be considered unless they are starting a MS or PHD program after graduating
• Visa Sponsorship is not available for this position. Candidates who now or at any point in the future require sponsorship for employment visa status (e.g., H-1B Visa status) may not be considered
• Strong Interest in semiconductor design, ASIC development, hardware verification, or Design-for-Test (DFT) methodologies
• Familiarity with Verilog, SystemVerilog, or VHDL