Sunnyvale, California
ASIC Engineering Intern, Design Verification (Silicon Engineering)
Job details
- Location
- Sunnyvale, California
- Work type
- Onsite
- Compensation
- $79,920 - $144,168/yr
- Posted
- 2 weeks ago
- Apply on
- metacareers.com
About this role
Currently pursuing a Master's in Electrical/Computer Engineering or related field; coursework in digital logic design; experience with Verilog/SystemVerilog; programming in object-oriented language; Python scripting; must obtain work authorization; intent to return to degree program.
What you'll do at Meta:
- writing test benches
- building verification components
- running simulations
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