Clock Design & Architecture Intern

## At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team drives the development of future High-Bandwidth Memory (HBM) architectures, clocking methodologies, and system-level technologies that support next-generation AI, HPC, networking, and data-center applications. The team works across architecture, design, verification, product engineering, and ecosystem partnerships to advance memory performance and design innovation. As an Intern, you will work with experienced architects and engineers to evaluate HBM clocking architectures, PLL performance, timing behavior, and clock distribution strategies. This role offers opportunities to apply analytical and modeling techniques while using AI-assisted engineering workflows to improve design exploration and productivity. ## Responsibilities - Analyze and document HBM clocking architectures, including clock distribution networks, WDQS timing architecture, and PLL design concepts. - Evaluate clock noise sensitivity, timing margins, jitter performance, and PLL impacts on high-speed IO signal quality. - Benchmark and compare alternative clock architecture solutions and provide data-driven recommendations. - Find opportunities for performance optimization and support architecture-level design decisions. - Apply Large Language Models (LLMs), Generative AI, and AI-assisted engineering workflows to enhance engineering analysis, data evaluation, and productivity. ## Minimum Qualifications - Currently pursuing a Master's or Ph.D. degree in Electrical Engineering or a related technical discipline. - Solid understanding of analog and mixed-signal circuit fundamentals. - Familiarity with clock generation and distribution concepts, including PLLs, DLLs, jitter, and timing analysis. - Experience using circuit simulation tools such as SPICE, Spectre, HSPICE, MATLAB, or equivalent technologies. - Strong analytical, debugging, problem-solving, written, and verbal communication skills. ## Preferred Qualifications - Understanding of timing analysis, clock quality metrics, signal integrity, and power integrity fundamentals. - Exposure to Generative AI, Large Language Models (LLMs), or AI-assisted engineering workflows used for engineering productivity and data analysis. - Coursework or research related to analog/mixed-signal design, PLLs, timing analysis, clocking systems, or high-speed interfaces. - Experience with Python or similar scripting languages for automation and data analysis. - Familiarity with semiconductor design methodologies, architecture evaluation, or high-speed memory systems.