Design for Test Intern - MS

## About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. ## Your Team, Your Impact The Compute and Custom Solutions (CCS) Business Unit within Marvell develops cutting-edge SoCs and processors in advanced process nodes for some of the largest companies in the world. We develop silicon solutions for the growing data center, enterprise, wireless, and automotive compute markets, collaborating with strategic customers from architecture and design all the way through layout, packaging, prototype validation, and production ramp-up. The CCS DFT (Design for Test) team is a key part of Marvell's global DFT community, with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology, and design. The team provides technology development, EDA/methodology development, and IP/chip design development. As an intern, you will be working with this team to directly enable customer DFT requirements in the CCS BU, gaining hands-on experience with industry-leading tools and methodologies used to build some of the world's most complex SoCs. ## What You Can Expect - Develop understanding of the block level or chip top DFT and pattern generation flows for complex SOC designs - Execute DFT insertion, pattern generation and verification flows for Scan, Memory Built-in Self-Test (MBIST), Boundary Scan and IP macro test - Run DFT checks and analyze results to resolve testability issues and improve DFT coverage - Support DFT flow automation through scripting (Tcl, Python, or shell) to improve design flows - Contribute to DFT documentation, methodology improvements and automation - Present intern project results to the team at the end of the internship ## What We're Looking For - Currently pursuing a Masters in Computer Engineering, Electrical Engineering, or related fields - Good understanding of digital logic design using Verilog/System Verilog - Knowledge of DFT concepts, JTAG standards and Boundary scan implementation - Knowledge of Scan test, memory BIST/BISR, functional test, JTAG, and other test methodologies is a plus - Experience in programming and scripting languages such as Python, Shell, Tcl - Knowledge of using AI assisted tools for coding, scripts and automation is a plus - Effective teamwork and communication skills