Digital Design Engineer

Qorvo, Inc. supplies semiconductor solutions for markets including consumer electronics, automotive, network infrastructure, healthcare, and aerospace/defense. The Digital Design Engineer will develop and verify digital control logic for mobile phone LNAs, TX controllers, and switches, including synthesis, physical design, timing closure, simulation, and scripting automation.

What you'll do:

• Verilog design of digital control logic for mobile phone LNAs, TX controllers and switches
• This specifically involves working with and/or having knowledge of design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus are required; RTL-to-GDS flow, area optimization, and DRC/LVS error resolution; digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL; Verilog digital design and verification and understanding of Verilog/System Verilog syntax; understanding of verification test benches, clocking and auto-checking; performing verification on the Verilog code using simulation tools; and Python scripting and other scripting languages
• Additionally, responsibilities include the creation of test benches and verification through simulation of the above designs using Xcelium, Verilog and Python automation; constraint creation and synthesis of mobile phone digital circuit designs with Cadence Genus, Conformal; and physical design and timing closure of mobile phone digital circuit designs with Cadence Innovus
• Further, the responsibilities include script automation development with Python to aid in the design of Qorvo’s mobile designs
• Hybrid: 3 days in the office and 2 work from within reasonable commuting distance from the office

What they're looking for:

• Master's degree in Electrical Engineering and 6 months of experience, an internship, co-op, or 6 graduate credit hours to involve knowledge of: (1) design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus are required; RTL-to-GDS flow, area optimization, and DRC/LVS error resolution; (3) digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL; (4) Verilog digital design and verification and understanding of Verilog/System Verilog syntax; (5) understanding of verification test benches, clocking and auto-checking; (6) performing verification on the Verilog code using simulation tools; and (7) Python scripting and other scripting languages
• Hybrid: 3 days in the office and 2 work from within reasonable commuting distance from the office
• This position is not eligible for visa sponsorship by the Company

Benefits:

• Hybrid work arrangement: 3 days in the office and 2 days working from within reasonable commuting distance from the office.