Digital Physical Design (P&R) Intern

NXP Semiconductors is a leading global semiconductor company, and they are seeking a Digital Physical Design Intern. In this role, you will join a highly experienced team and be responsible for understanding existing flows and tools, supporting experiments with RTL implementations, and suggesting improvements to enhance backend flow efficiency.

What you'll do:

• Understand the existing flow, tools and scripts to do Digital backend flow from Synthesis to GDS2 using Cadence tools
• Support with multiple parallel runs to experiment with different RTL implementations, and/or tools options to find the most area-optimal solution
• Deeply study the Cadence tools’ user-manuals and user-forum discussions, and suggest improvements to existing flows and scripts that could improve the quality and efficiency of the backend flow

What they're looking for:

• Pursuing Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL, Digital backend flow
• Willing to relocate to Phoenix Metro area (Arizona) for the full duration of internship, and minimum 3 days per week full-day presence in NXP's Chandler office
• Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills
• Any prior experience with this flow is a strong plus