Graduate Digital Design Engineer

## The Role We are seeking a talented and motivated Graduate Digital Design Engineer to join our team and contribute to the design and verification of digital and mixed-signal IP for our chiplet solutions, including PCS (Physical Coding Sublayer) logic and custom high-speed interfaces such as UCIe, Ethernet and PCIe. Working alongside experienced digital and analog engineers, you will write RTL, build testbenches and behavioural models, and see your work go into customer silicon. This role is well suited to recent graduates with a strong foundation in digital design who want to learn fast through hands-on work in a small, high-impact team. Hiring Manager: Christian Borelli, Founder and CSO. ## Key Responsibilities - RTL Design: Design and implement digital blocks for PCS and interface IP (e.g. encoders/decoders, scramblers, PRBS generators/checkers, FIFOs, CDC logic, control and calibration state machines) in Verilog/SystemVerilog, under the guidance of senior designers. - Standards & Specifications: Study SerDes and UCIe standards and architecture documents, and help turn them into clear block-level specifications. - Verification: Build testbenches and run simulations to verify your designs, using SystemVerilog, UVM or cocotb, and help develop verification plans and coverage. - Mixed-Signal Modelling: Write behavioural models of analog blocks in Verilog/SystemVerilog (and Verilog-A where needed) to support mixed-signal and top-level simulation with the analog team. - Implementation Support: Gain exposure to synthesis, lint, CDC checks and static timing analysis, and learn how design choices affect power, performance and area. - Scripting & Automation: Use scripting (e.g. Python, TCL or shell) to automate simulation, regression and reporting flows. - Documentation & Process: Document your designs and test results clearly, and contribute ideas to improve our design and verification environments and procedures. - Collaboration: Work closely with an experienced team of digital, analog and layout engineers across products such as UCIe, Ethernet and PCIe. ## Must-Have Requirements - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field (recent graduates and those graduating within the next 6 months are welcome) - 0–2 years of experience in digital design, including internships, placements or university projects - Solid understanding of digital logic fundamentals: synchronous design, finite state machines, timing, pipelining and clock-domain crossing - Hands-on experience writing RTL in Verilog or SystemVerilog, through coursework, thesis, FPGA or internship projects - Experience with an HDL simulator (e.g. Xcelium, VCS, Questa or open-source tools such as Verilator or Icarus) - Excellent problem-solving skills and attention to detail ## Nice-to-Have - Exposure to verification methodologies such as UVM, SystemVerilog assertions or cocotb - Basic knowledge of synthesis, static timing analysis or place-and-route - Familiarity with high-speed serial interfaces or protocols (e.g. UCIe, Ethernet, PCIe) or line coding (e.g. 8b/10b, 64b/66b) - Awareness of Design-for-Test concepts (scan, BIST) and hardware/software co-design - Scripting skills in Python, TCL or shell, and comfort in a Linux environment - FPGA prototyping experience ## Soft and Professional Skills - Clear, structured communication in professional English, able to explain complex results concisely - Collaborative and feedback-oriented mindset - Demonstrated ability to mentor and guide less experienced engineers - Strong ownership, reliability, and follow-through - Curious, self-motivated attitude, eager to learn and explore new tools or methods - High level of integrity and professionalism in representing the company and handling sensitive information ## Our Culture We are a fully remote team of around 45 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. Our values are: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them. - Connected, even remotely: regular all-hands, 1:1s, technical reviews, and informal coffee chats. - High ownership, real impact: everyone contributes directly to customer-facing IP. - How we work: we move fast but thoughtfully, communicate openly, and balance autonomy with support. ## Why Join Us - Remote-first flexibility: work from anywhere, with flexible hours - Equipment and setup provided - High-impact projects designing real digital and mixed-signal IP used in customer silicon, from your first months - Mentorship from day one with a dedicated manager and experienced engineers - Competitive, transparent compensation adjusted for your location and engagement model - Learning and growth: structured onboarding, AI-DLP sessions, technical deep dives, and peer-led knowledge sharing ## Recruitment Process - Founder Call (30 min) - Technical Interview (90 min) - Optional: Second Technical Interview (60 min) - HR and Culture Call (45 min) - Offer and Next Steps