IC Layout Engineering Intern

Qorvo supplies innovative semiconductor solutions across consumer electronics, automotive, infrastructure, healthcare, and aerospace/defense markets. The IC Layout Engineering Intern will support physical implementation and verification of RF, analog, and mixed-signal circuit blocks while learning semiconductor layout methodologies, design tools, and technologies. The role also involves documentation, tapeout activities, technical reviews, and collaboration with engineering teams.

What you'll do:

• Complete physical implementation of RF, analog, and mixed signal circuit blocks
• Learn and apply foundry PDK design rules and layout methodologies
• Support block level floor planning and device placement activities
• Perform layout edits using Cadence Virtuoso and other industry standard EDA tools
• Execute basic verification checks including DRC, LVS, and ERC
• Participate in debugging and resolving verification issues
• Assist in maintaining clean and organized version control practices
• Document layout activities, verification results, and project milestones
• Tapeout activities, including generation of GDS files and documentation packages
• Learn about different semiconductor technologies (GaAs, Silicon, and GaN) and best practices such as matching, symmetry, shielding, guard rings, and routing techniques
• Participate in technical reviews, team meetings, and engineering training sessions

What they're looking for:

• Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Physics, or a related technical discipline
• Minimum GPA of 3.0 or equivalent academic standing
• Basic understanding of semiconductor devices and integrated circuits
• Coursework in analog circuits, digital circuits, VLSI design, semiconductor devices, or microelectronics
• Strong analytical, problem solving, written and verbal communication skills
• Ability to work collaboratively in a team environment
• Coursework or projects involving IC physical design or VLSI layout
• Familiarity with Cadence Virtuoso or similar IC design tools
• Basic knowledge of Linux operating systems
• Exposure to scripting languages such as Python, SKILL, Perl, or Shell scripting
• Understanding of layout verification concepts such as DRC and LVS
• This position is not eligible for visa sponsorship by the Company

Benefits:

• Challenging, skill-building assignments
• Mentoring and coaching from industry experts
• Launch & Learns and other learning opportunities
• Collaborative team-based work environment
• Networking and social events
• Final presentation to business leaders