Astranis
San Francisco, California
PCB Layout Engineer Intern (Fall 2026)
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Apply to PCB Layout Engineer Intern (Fall 2026) at AstranisJob details
- Location
- San Francisco, California
- Work type
- Onsite
- Compensation
- $60,320/yr
- Posted
- Jul 1, 2026
- Apply on
- job-boards.greenhouse.io
About this role
Currently enrolled EE student; familiar with Altium/ECAD; basic analog, RF, power and digital electronics knowledge; US citizen or lawful permanent resident required.
What you'll do at Astranis:
- placing PCBs
- routing PCBs
- creating footprints
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