San Jose, California
Principal Analog IC Design Engineer, High Speed SerDes
Job details
- Location
- San Jose, California
- Work type
- Onsite
- Compensation
- $136,500 - $253,500/yr
- Posted
- Aug 13, 2026
- Apply on
- cadence.wd1.myworkdayjobs.com
About this role
Minimum 7 years in CMOS SerDes or high-speed I/O IC design; MS or PhD in electrical engineering; analog/mixed-signal design, verification, CAD tools, and circuit simulation experience required.
What you'll do at Cadence:
- designing circuits
- verifying designs
- simulating circuits
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