RTL Digital Design Intern

## Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional RTL Digital Design Intern to join the Memory Interface Chip BU's engineering team in Johns Creek, Georgia. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a RTL Digital Design Intern, you will be reporting to the Digital Design Director of Engineering and working closely with highly experienced engineers to complete an assignment within the DDR6 memory interface design team working on silicon products within AI data centers. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. ## Responsibilities - Develop Verilog/SystemVerilog RTL for next-generation DDR5/DDR6 memory interface products. Learn and contribute to cutting-edge DDR5/DDR6 memory interface architectures and protocols. - Design digital control logic, state machines, and register interfaces. - Analyze and optimize RTL designs for power, performance, and area (PPA). - Support timing closure and Static Timing Analysis (STA). - Create behavioral models for simulation and verification. - Work closely with verification and validation teams during silicon bring-up and debug. ## Qualifications - BS or MS in Electrical Engineering or Computer Engineering. - Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms. - Background in digital RTL design including standard LEC, CDC, Lint, DFT, BIST, and STA tools. - High aptitude with Verilog and SystemVerilog. - Ability to document design techniques, test, and verification methodologies. - Python/Perl script development. - Strong debugging, analytical, and communication skills.