OpenAI
San Francisco, California
Senior RTL Engineer, Interconnect Design
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Apply to Senior RTL Engineer, Interconnect Design at OpenAIJob details
- Location
- San Francisco, California
- Work type
- Hybrid
- Compensation
- $225,000 - $445,000/yr
- Posted
- 4 weeks ago
- Apply on
- jobs.ashbyhq.com
About this role
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
What you'll do at OpenAI:
- owning interconnect
- designing RTL
- mentoring engineers
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