Silicon Design Manager, RTL Machine Learning, Accelerator Design

Bachelor's degree in EE, CE, CS or equivalent; 10 years chip design and SystemVerilog; 8 years computer architecture and RTL; 3 years people management; US work authorization not stated.

What you'll do at Google:

• managing RTL engineers
• providing technical leadership
• collaborating with cross-functional teams

Apply to this Silicon Design Manager, RTL Machine Learning, Accelerator Design role at Google with a tailored resume on ApplyBolt.